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FM25C160U 16K-Bit SPI Interface Serial CMOS EEPROM
February 2002
FM25C160U 16K-Bit SPITM Interface Serial CMOS EEPROM
General Description
The FM25C160U is a 16K bit serial interface CMOS EEPROM (Electrically Erasable Programmable Read-Only Memory). This device fully conforms to the SPI 4-wire protocol which uses Chip Select (/CS), Clock (SCK), Data-in (SI) and Data-out (SO) pins to synchronously control data transfer between the SPI microcontroller and the EEPROM. In addition, the serial interface allows a minimal pin count, packaging designed to simplify PC board layout requirements and offers the designer a variety of low voltage and low power options. This SPI EEPROM family is designed to work with the 68HC11 or any other SPI-compatible, high-speed microcontroller and offers both hardware (/WP pin) and software ("block write") data protection. For example, entering a 2-bit code into the STATUS REGISTER prevents programming in a selected block of memory and all programming can be inhibited by connecting the /WP pin to VSS; allowing the user to protect the entire array or a selected section. In addition, SPI devices feature a /HOLD pin, which allows a temporary interruption of the datastream into the EEPROM. Fairchild EEPROMs are designed and tested for applications requiring high endurance, high reliability, and low power consumption for a continuously reliable non-volatile solution for all markets.
Functions
I SPI MODE 0 interface I 16K bits organized as 2048 x 8 I Extended 2.7V to 5.5V operating voltage I 2.1 MHz operation @ 4.5V - 5.5V I Self-timed programming cycle I "Programming complete" indicated by STATUS REGISTER polling I /WP pin and BLOCK WRITE protection
Features
I Sequential read of entire array I 16 byte "Page write" mode to minimize total write time per byte I /WP pin and BLOCK WRITE protection to prevent inadvertent programming as well as programming ENABLE and DISABLE opcodes. I /HOLD pin to suspend data transfer I Typical 1A standby current (ISB) for "L" devices and 0.1A standby current for "LZ" devices. I Endurance: Up to 1,000,000 data changes I Data retention greater than 40 years
Block Diagram
/CS /HOLD SCK SI Instruction Register Instruction Decoder Control Logic and Clock Generators VCC VSS /WP
Address Counter/ Register
Program Enable VPP
High Voltage Generator and Program Timer
Decoder
EEPROM Array
Read/Write Amps
Data In/Out Register 8 Bits
Data Out Buffer
SO
Non-Volatile Status Register
SPITM is a trademark of Motorola Corporation
(c) 2002 Fairchild Semiconductor Corporation FM25C160U Rev. B
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FM25C160U 16K-Bit SPI Interface Serial CMOS EEPROM
Connection Diagram
Dual-In-Line Package (N) and SO Package (M8) /CS SO /WP VSS 1 2 FM25C160U 3 4 6 5 SCK SI 8 7 VCC /HOLD
Top View See Package Number N08E (N) and M08A (M8)
Pin Names
/CS SO /WP VSS SI SCK /HOLD VCC Chip Select Input Serial Data Output Write Protect Ground Serial Data Input Serial Clock Input Suspends Serial Data Power Supply
Ordering Information FM 25 C XX U LZ E XX
Package Temp. Range
Letter Description
N M8 None V E Blank L LZ Ultralite Density/Mode Interface 160 C 25 FM 8-pin DIP 8-pin SO 0 to 70C -40 to +125C -40 to +85C 4.5V to 5.5V 2.7V to 5.5V 2.7V to 5.5V and <1A Standby Current CS100UL Process 16K, mode 0 CMOS technology SPI Fairchild Nonvolatile Memory Prefix
Voltage Operating Range
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FM25C160U Rev. B
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FM25C160U 16K-Bit SPI Interface Serial CMOS EEPROM
Standard Voltage 4.5 VCC 5.5V Specifications Operating Conditions Absolute Maximum Ratings (Note 1)
Ambient Storage Temperature All Input or Output Voltage with Respect to Ground Lead Temp. (Soldering, 10 sec.) ESD Rating -65C to +150C +6.5V to -0.3V +300C 2000V Ambient Operating Temperature FM25C160U FM25C160UE FM25C160UV Power Supply (VCC) 0C to +70C -40C to +85C -40C to +125C 4.5V to 5.5V
DC and AC Electrical Characteristics 4.5V VCC 5.5V (unless otherwise specified)
Symbol
ICC ICCSB IIL IOL VIL VIH VOL VOH fOP tRI tFI tCLH tCLL tCSH tCSS tDIS tHDS tCSN tDIN tHDN tPD tDH tLZ tDF tHZ tWP
Parameter
Operating Current Standby Current Input Leakage Output Leakage CMOS Input Low Voltage CMOS Input High Voltage Output Low Voltage Output High Voltage SCK Frequency Input Rise Time Input Fall Time Clock High Time Clock Low Time Min /CS High Time /CS Setup Time Data Setup Time /HOLD Setup Time /CS Hold Time Data Hold Time /HOLD Hold Time Output Delay Output Hold Time /HOLD to Output Low Z Output Disable Time /HOLD to Output High Z Write Cycle Time
Conditions
/CS = VIL /CS = VCC VIN = 0 to VCC VOUT = GND to VCC
Min
Max
3 50
Units
mA A A A V V V V MHz s s ns ns ns ns ns ns ns ns ns
-1 -1 -0.3 0.7 * VCC
+1 +1 VCC * 0.3 VCC + 0.3 0.4
IOL = 1.6 mA IOH = -0.8 mA VCC - 0.8
2.1 2.0 2.0 (Note 2) (Note 2) (Note 3) 190 190 240 240 100 90 240 100 90 CL = 200 pF 0 100 CL = 200 pF 1-16 Bytes 240 100 10 240
ns ns ns ns ns ms
Capacitance TA = 25C, f = 2.1/1 MHz (Note 4)
Symbol
COUT CIN
AC Test Conditions
Output Load Input Pulse Levels Timing Measurement Reference Level CL = 200 pF 0.1 * VCC - 0.9 * VCC 0.3 * VCC - 0.7 * VCC
Test
Output Capacitance Input Capacitance
Typ Max Units
3 2 8 6 pF pF
Note 1: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For example, for a fOP of 2.1MHz, the period equals 476ns. In this case if t CLH = is set to 190ns, then tCLL must be set to a minimum of 286ns. Note 3: /CS must be brought high for a minimum of tCSH between consecutive instruction cycles. Note 4: This parameter is periodically sampled and not 100% tested.
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FM25C160U 16K-Bit SPI Interface Serial CMOS EEPROM
Low Voltage 2.7V VCC 4.5V Specifications Operating Conditions Absolute Maximum Ratings (Note 5)
Ambient Storage Temperature All Input or Output Voltage with Respect to Ground Lead Temp. (Soldering, 10 sec.) ESD Rating -65C to +150C +6.5V to -0.3V +300C 2000V Ambient Operating Temperature FM25C160UL/LZ FM25C160ULE/LZE FM25C160ULV Power Supply (VCC) 0C to +70C -40C to +85C -40C to +125C 2.7V-4.5V
DC and AC Electrical Characteristics 2.7V VCC 4.5V (unless otherwise specified)
25C160UL/LE 25C160ULZ/ZE Symbol
ICC ICCSB IIL IOL VIL VIH VOL VOH fOP tRI tFI tCLH tCLL tCSH tCSS tDIS tHDS tCSN tDIN tHDN tPD tDH tLZ tDF tHZ tWP
25C160ULV Min Max
3 10 N/A -1 -1 -0.3 VCC * 0.7 VCC - 0.8 1 1 VCC * 0.3 VCC + 0.3 0.4 1.0 2.0 2.0 410 410 500 500 100 240 500 100 240
Parameter
Operating Current Standby Current Input Leakage Output Leakage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage SCK Frequency Input Rise Time Input Fall Time Clock High Time Clock Low Time Min. /CS High Time /CS Setup Time Data Setup Time /HOLD Setup Time /CS Hold Time Data Hold Time /HOLD Hold Time Output Delay Output Hold Time /HOLD Output Low Z Output Disable Time /HOLD to Output Hi Z Write Cycle Time
Part
L LZ
Conditions
/CS = VIL /CS = VCC VIN = 0 to VCC VOUT = GND to VCC
Min.
Max.
3 10 1
Units
mA A A A A V V V V MHz s s ns ns ns ns ns ns ns ns ns
-1 -1 -0.3 VCC * 0.7
1 1 VCC * 0.3 VCC + 0.3 0.4
IOL = 0.8 mA IOH = -0.8 mA VCC - 0.8
1.0 2.0 2.0 (Note 6) (Note 6) (Note 7) 410 410 500 500 100 240 500 100 240 CL = 200 pF 0 240 CL = 200 pF 1-16 Bytes 500 240 15 500 0
500 240 500 240 15
ns ns ns ns ns ms
Capacitance TA = 25C, f = 2.1/1 MHz (Note 8)
Symbol
COUT CIN
AC Test Conditions
Output Load Input Pulse Levels Timing Measurement Reference Level CL = 200pF 0.1 * VCC - 0.9 * VCC 0.3 * VCC - 0.7 * VCC
Test
Output Capacitance Input Capacitance
Typ Max Units
3 2 8 6 pF pF
Note 5: Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 6: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For example, for a fOP of 1MHz, the period equals 1000ns. In this case if tCLH = is set to 410ns, then tCLL must be set to a minimum of 590ns. Note 7: /CS must be brought high for a minimum of tCSH between consecutive instruction cycles. Note 8: This parameter is periodically sampled and not 100% tested.
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FM25C160U 16K-Bit SPI Interface Serial CMOS EEPROM
FIGURE 1. Synchronous Data Timing Diagram
tCSI
/CS
tCSS tCLH tCLL tCSH
Mode 3 SCK Mode 0
Mode 3 Mode 0
tDIS
tDIH
SI
Valid Input
tPD
tDH
tDF
SO
Valid Output
High Z
FIGURE 2. SPI Protocol
/CS Mode 3 Mode 3
SCK
SI
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Don't Care
SO
High Z
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FIGURE 3. HOLD Timing
CS
tHDS tHDH Low state ( /CS = 0) tHDS tHDH
SCK
Don't Care
/HOLD
tHZ tLZ High Z tDIS
SO
Output (n+2)
Output (n+1)
Output (n)
Output (n)
SI
Input (n+2)
Input (n+1)
Input (n)
Don't Care
Input (n)
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FM25C160U 16K-Bit SPI Interface Serial CMOS EEPROM
Pin Description
Chip Select (/CS)
This is an active low input pin to the EEPROM and is generated by a master that is controlling the EEPROM. A low level on this pin selects the EEPROM and a high level deselects the EEPROM. All serial communications with the EEPROM is enabled only when this pin is held low.
Functional Description
The Serial Peripheral Interface (SPI) of FM25C160U consists of an 8-bit Instruction register to decode a specific instruction to be executed. Six different instructions (Opcodes) are incorporated on FM25C160U for various operations. Table2 lists the instructions set and the format for proper operation. All Opcodes, Array addresses and Data are transferred in "MSB first-LSB last" fashion. Detailed information is provided under individual instruction descriptions.
Serial Clock (SCK)
This is an input pin to the EEPROM and is generated by the master that is controlling the EEPROM. This is a clock signal that synchronizes the communication between a master and the EEPROM. All input information (SI) to the EEPROM is latched on the rising edge of this clock input, while output data (SO) from the EEPROM is driven after the falling edge of this clock input.
TABLE 2. Instruction Set Instruction Instruction Name Opcode
WREN WRDI RDSR WRSR READ WRITE 00000110 00000100 00000101 00000001 00000011 00000010
Operation
Write Enabled Write Disabled Read Status Register Write Status Register Read Data from Memory Array Write Data to Memory Array
Serial Input (SI)
This is an input pin to the EEPROM and is generated by the master that is controlling the EEPROM. The master transfers Input information (Instruction Opcodes, Array addresses and Data) serially via this pin into the EEPROM. This Input information is latched on the rising edge of the SCK.
Serial Output (SO)
This is an output pin from the EEPROM and is used to transfer Output data via this pin to the controlling master. Output data is serially shifted out on this pin after the falling edge of the SCK.
Hold (/HOLD)
This is an active low input pin to the EEPROM and is generated by the master that is controlling the EEPROM. When driven low, this pin suspends any current communication with the EEPROM. The suspended communication can be resumed by driving this pin high. This feature eliminates the need to re-transmit the entire sequence by allowing the master to resume the communication from where it was left off. This pin should be tied high if this feature is not used. Refer Hold Function description for additional details.
In addition to the Instruction register, FM25C160U also contains an 8-bit Status register that can be accessed by RDSR and WRSR instructions. Only the least significant (LSB) 4 bits are defined at present and the most significant (MSB) 4 bits are undefined (don't care). The LSB 4 bits define Block Write Protection levels (BP1and BP0), Write-enable status (WEN) and Busy/Rdy status (/RDY) of the EEPROM. Table 3 illustrates the format:
TABLE 3. Status Register Format
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
BP1
Bit 2
BP0
Bit 1
WEN
Bit 0
RDY
Write Protect (/WP)
This is an active low input pin to the EEPROM. This pin allows enabling and disabling of writes to memory array and status register of the EEPROM. When this pin is held low, writes to the memory array and status register are disabled. When this pin is held high, writes to the memory array and status register are enabled. Status of this pin does not affect operations other than array write and status register write. /WP signal going low at any time will inhibit programming, except when an internal write has already begun. If an internal write cycle has already begun, /WP signal going low will have no effect on the write. Refer Table1 for Write Protection matrix.
Refer RDSR and WRSR instruction descriptions for additional information on Status register operations.
Table1. Write Protection Matrix /WP Pin
Low High High
WEN Bit
X 0 1
Status Register
Write Protected Write Protected Write Allowed
Protected Blocks (by BP1-BP0)
Write Protected Write Protected Write Protected
Unprotected Blocks
Write Protected Write Protected Write Allowed
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FM25C160U 16K-Bit SPI Interface Serial CMOS EEPROM
Functional Description (Continued)
SPI communication
As mentioned before, serial communication with the EEPROM is enabled when the /CS pin is held low and the /HOLD pin is held high. Input data (Instruction Opcodes, Array addresses and Data) on the SI pin is latched in on the rising edges of SCK clock signal, starting from the first rising edge after the /CS pin goes low. During the time the SI data is input into the EEPROM, the SO pin remains in high impedance state. If the intended instruction is of read nature (Array read and Status register read), then data from the EEPROM is driven out actively on the SO pin from every falling edge of the SCK after the last input data (SI) is latched in. During the time the SO data is output from the EEPROM, the data on the SI pin is ignored. Figure 2 illustrates the above. Refer Figure 1 for timing information.
SPI Modes 0 and 3 (00 and 11)
FM25C160U supports both Mode 0 and Mode 3 of operations. The difference between Mode 0 and Mode 3 is determined by the state of the SCK clock signal when a SPI cycle starts (when /CS is driven low) as well as when the SPI cycle ends (when /CS is driven high). Under Mode 0 of operation, the SCK signal is held low both at the start and at the end of a SPI cycle. Under Mode 1 of operation, the SCK signal is held high both at the start and at the end of a SPI cycle. However in both of these two modes, the input data (SI) is sampled (latched in) at the rising edge of the SCK clock signal and the output data (SO) is driven after the falling edge of the SCK clock signal. See Figure 1 and Figure 2.
READ SEQUENCE (READ)
Reading the memory via the serial SPI link requires the following sequence. The/CS pin is pulled low to select the EEPROM. The READ opcode is transmitted on the SI pin followed by two bytes of address, "High byte addr" (A15-A8) and "Low byte addr" (A7-A0). After this is done, data on the SI pin becomes don't care. The data (D7-D0) form the address specified is then shifted out on the SO pin. If only one byte is to be read, the /CS pin can be pulled back to the high level. It is possible to continue the READ sequence as the byte address is automatically incremented and data will continue to be shifted out as clock pulses are continuously applied. When the end of memory array is reached (last byte location), the address counter rolls over to the start of memory array (first byte location) allowing the entire memory to be read in one continuous READ cycle. See Figure 5. Note that only A10-A0 address bits are treated valid by FM25C160U while bits A15-A11 are ignored.
HOLD function
An active communication with the EEPROM can be temporarily suspended by bringing the /HOLD pin low when a EEPROM is selected (/CS pin should be low) and a serial sequence with the EEPROM is currently underway. To suspend the communication, /HOLD pin must be driven low while SCK is low, otherwise the Hold function will not be invoked until the next SCK high to low transition. The EEPROM must remain selected during this sequence. Transitions on the SCK and SI pins are ignored during the time the part is suspended and the SO pin will be in high impedance state. Releasing the /HOLD pin back to high state will allow the operation to resume from the point it was suspended. /HOLD pin must be driven high while the SCK pin is low, otherwise serial communication will not resume until the next SCK high to low transition. Asserting a low on the /HOLD pin at any time will tristate the SO pin. Figure 3 illustrates Hold timing.
System Configuration
When multiple SPI peripherals (for e.g. EEPROMs) are present on the bus, the SI, SO and the SCK signals can be tied together. Figure 4 illustrates a typical system configuration with respect to /CS, SCK, SI and SO pins.
FIGURE 4. System Configuration
MASTER MCU DATA OUT (MOSI) DATA IN (MISO) SERIAL CLOCK (SPICK) SS0 FM25Cxxx
;;;;;
FIGURE 5. Read Sequence
CS SI Read Opcode High Byte Addr Low Byte Addr SO Data (1) Data (2) Data (n)
READ STATUS REGISTER (RDSR):
SI SO SCK /CS SI SO SCK /CS SI SO SCK /CS SI SO SCK /CS
The Read Status Register (RDSR) instruction provides read access to the status register. As mentioned before, of the 8bits of data, only the LSB 4bits are valid and they indicate Block Protection information (BP1 and BP0), Write Enable status (WEN) and Busy/Ready status (/RDY) of the EEPROM. MSB 4bits of are invalid (Don't cares) Following is the format of RDSR data:
TABLE 3. Status Register Format
Bit 7
X
SPI CHIP SELECTION
SS1 SS2 SS3
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
BP1
Bit 2
BP0
Bit 1
WEN
Bit 0
RDY
Bit3 (BP1) and Bit2 (BP0) together indicate Block write protection previously set on the EEPROM. Refer Table 2. Bit1 (WEN) indicates the Write enable status of the EEPROM. This bit is a read-only bit and is read by executing RDSR instruction. If this bit is "1" then the EEPROM is write enabled. If this bit is "0" then the EEPROM is write disabled.
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FM25C160U 16K-Bit SPI Interface Serial CMOS EEPROM
Bit0 (/RDY) indicates the Busy/Ready status of the EEPROM. This bit is a read-only bit and is read by executing RDSR instruction. If this bit is "1" then the EEPROM is busy doing a program cycle. If this bit is "0" then the EEPROM is ready. Note that if a RDSR instruction is executed when an internal programming cycle is in progress, only the /RDY bit is valid. All other bits are don't cares. The RDSR command requires the following sequence. The /CS pin is pulled low to select the EEPROM and then the RDSR opcode is transmitted on the SI pin. After this is done, data on the SI pin becomes don't care. The data from the Status Register is then shifted out on the SO pin starting with D7 bit first and D0 last. See Figure 6.
WRITE SEQUENCE (WRITE):
Write to the array is enabled only when /WP pin is held high and the EEPROM is write enabled previously (via WREN instruction). Also, the address of the memory location(s) to be programmed must be outside the protected address field selected by the Block Write Protection Level. See Table 4.
TABLE 4. Block Write Protection Levels
Level
0 1 2 3
Status Register Bits BP1
0 0 1 1
BP0
0 1 0 1
Array Address Protected
None 600-7FF 400-7FF 000-7FF
FIGURE 6. Read Status Register
/CS
SI
RDSR OP-CODE
SO
RDSR DATA
WRITE ENABLE (WREN):
When VCC is applied to the EEPROM, it "powers up" in a writedisabled state. Therefore, all programming modes (Write to memory array and Status register), must be preceded by a WRITE ENABLE (WREN) instruction. See Figure 7.
FIGURE 7. Write Enable
/CS
SI
WREN Op-Code
;;;;
FIGURE 9. Byte Write
CS SI Write Opcode High Addr Byte Low Addr Byte Data SO
A WRITE command requires the following sequence. The /CS pin is pulled llow to select the EEPROM, then the WRITE opcode is transmitted on the SI pin followed by two bytes of address, "High byte addr" (A15-A8) and "Low byte addr" (A7-A0), further followed by the data (D7-D0) to be written. See Figure 9. Note that only A10A0 address bits are treated valid by FM25C160U while bits A15A11 are ignored.
High Z
Internally, the programming will start after the /CS pin is brought back to a high level. Note that the LOW to HIGH transition of the /CS pin must occur during the SCK low time immediately after clocking in the D0 data bit. See Figure 10.
SO
WRITE DISABLE (WRDI):
Executing this instruction disables all programming modes (Write to memory array and Status register), preventing the EEPROM from accidental writes. Once WRDI instruction is executed, WREN instruction should be executed to re-enable all programming modes. See Figure 8.
FIGURE 10. Start of Programming
/CS
Start of internal programming
SCK
FIGURE 8. Write Disable
SI D2 D1 D0
/CS
SO
High Z
SI
WRDI Op-Code
SO
Programming status (Busy/Ready) of the EEPROM can be determined by executing a READ STATUS REGISTER (RDSR) instruction after a write command. Upon executing the RDSR instruction, if Bit 0 of the RDSR data is "1", it indicates the WRITE cycle is still in progress. If it is "0" then the WRITE cycle has ended. Note that while the internal programming is still in progress (Bit 0 = 1), only the RDSR instruction is enabled. It is recommended that no other instruction be issued till the internal programming is complete.
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FM25C160U 16K-Bit SPI Interface Serial CMOS EEPROM
The FM25C160U is also capable of a 16 byte PAGE WRITE operation. Page write is performed similar to byte write operation described above. During a Page write operation, after the first byte of data, additional bytes (up to 15 bytes) can be input, before bringing the /CS pin high to start the programming. After receipt of each byte of data, the EEPROM internally increments the four low order address bits (A3-A0) by one. The high order address bits (A10-A4) will remain constant. If the master should transmit more than 16 bytes of data, the address counter (A3-A0) will "roll over" and the previously loaded data will be reloaded. See Figure 11.
FIGURE 12. Write Status Register
/CS
SI
WRSR Op-Code
SR Data xxxxBP1BP0xx
FIGURE 11. Page Write
CS
SO
SI
Write Opcode
High Addr Byte
Low Addr Byte
Data (1)
Data (2)
Data (16)
Programming will start after the /CS pin is forced back to a high level. As in the WRITE instruction the LOW to HIGH transition of the /CS pin must occur during the SCK low time immediately after clocking in the last don't care bit. See Figure 13.
SO
High Z
FIGURE 13. Start WRSR Condition
/CS
At the completion of a write cycle the EEPROM is automatically returned to the write disabled state. Note that if the EEPROM is not write enabled (WEN=0) before issuing the WRITE instruction, the EEPROM will ignore the WRITE instruction and return to the standby state when /CS is brought high.
SCK
WRITE STATUS REGISTER (WRSR):
The Write Status Register (WRSR) instruction provides write access to the status register. This instruction is used to set Block Write protection to a portion of the array as defined under Table 4. During a WRSR instruction only Bit3 (BP1) and Bit2 (BP0) can be written with valid information while other bits are ignored. Following is the format of WRSR data:
SI BP0
SO
Status Register Write Data
Bit 7
X
X = Don't Care
At the completion of this instruction the EEPROM is automatically returned to write disabled state.
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
BP1
Bit 2
BP0
Bit 1
X
Bit 0
X
INVALID OPCODE
If an invalid code is received, then no data is shifted into the EEPROM, and the SO data output pin remains high impedance state until a new /CS falling edge reinitializes the serial communication. See Figure 14.
Note that the first four bits are don't care bits followed by BP1 and BP0 and two more don't care bits. WRSR instruction is enabled only when /WP pin is held high and the EEPROM is write enabled previously (via WREN instruction). WRSR command requires the following sequence. The /CS pin is pulled low to select the EEPROM and then the WRSR opcode is transmitted on the SI pin followed by the data to be programmed. See Figure 12.
FIGURE 14. Invalid Op-Code
/CS
SI
INVALID CODE
SO
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FM25C160U 16K-Bit SPI Interface Serial CMOS EEPROM
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197 (4.800 - 5.004)
8765
0.228 - 0.244 (5.791 - 6.198)
1234
Lead #1 IDENT 0.150 - 0.157 (3.810 - 3.988) 8 Max, Typ. All leads 0.004 (0.102) All lead tips
0.010 - 0.020 x 45 (0.254 - 0.508)
0.053 - 0.069 (1.346 - 1.753)
0.004 - 0.010 (0.102 - 0.254) Seating Plane
0.0075 - 0.0098 (0.190 - 0.249) Typ. All Leads
0.016 - 0.050 (0.406 - 1.270) Typ. All Leads
0.014 (0.356) 0.050 (1.270) Typ 0.014 - 0.020 Typ. (0.356 - 0.508)
Molded Small Out-Line Package (M8) Package Number M08A
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FM25C160U 16K-Bit SPI Interface Serial CMOS EEPROM
Physical Dimensions inches (millimeters) unless otherwise noted
0.373 - 0.400 (9.474 - 10.16) 0.090 (2.286) 0.092 DIA (2.337) Pin #1 IDENT Option 1 0.032 0.005
8
7
8
+
7
6
5
0.250 - 0.005 (6.35 0.127)
(0.813 0.127) RAD Pin #1 IDENT
1 1 2 3 4
0.039 (0.991) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 90 4 Typ 0.018 0.003 (0.457 0.076) 0.100 0.010 (2.540 0.254) 0.060 (1.524) 0.020 (0.508) Min Option 2 0.145 - 0.200 (3.683 - 5.080)
0.280 MIN (7.112) 0.300 - 0.320 (7.62 - 8.128)
0.040 Typ. (1.016) 0.030 MAX (0.762) 20 1
95 5 0.009 - 0.015 (0.229 - 0.381) +0.040 0.325 -0.015 +1.016 8.255 -0.381 0.125 (3.175) DIA NOM
0.065 (1.651)
0.045 0.015 (1.143 0.381) 0.050 (1.270)
Molded Dual-In-Line Package (N) Package Number N08E
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 Fairchild Semiconductor Europe Fax: +44 (0) 1793-856858 Deutsch Tel: +49 (0) 8141-6102-0 English Tel: +44 (0) 1793-856856 Francais Tel: +33 (0) 1-6930-3696 Italiano Tel: +39 (0) 2-249111-1
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Hong Kong 8/F, Room 808, Empire Centre 68 Mody Road, Tsimshatsui East Kowloon. Hong Kong Tel; +852-2722-8338 Fax: +852-2722-8383
Fairchild Semiconductor Japan Ltd. 4F, Natsume Bldg. 2-18-6, Yushima, Bunkyo-ku Tokyo, 113-0034 Japan Tel: 81-3-3818-8840 Fax: 81-3-3818-8841
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FM25C160U Rev. B
www.fairchildsemi.com

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